1) Field of the Invention
This invention relates generally to fabrication semiconductor memory devices and particularly to the structure of a one transistor (1T) Static Random Access Memory (SRAM) cell.
2) Description of the Prior Art
FIG. 1 shows a schematic of a one transistor (1T) Static Random Access Memory (SRAM) cell. The 1T SRAM is designed for high speed and low cost logic products. However, the inventors have found that the 1 T SRAM cell has performance degradation that can be reduced.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,686,336(Lee) shows a 4T SRAM layout. U.S. Pat. No. 6,078,087(Huang et al.) and U.S. Pat. No. 5,953,606(Huang et al.) shows TFT SRAM layouts.
It is an object of the present invention to provide a method for fabricating a 1T SRAM with low leakage.
It is an object of the present invention to provide a method for fabricating a 1T SRAM with low leakage using a P minus (Pxe2x88x92) region on the cell storage node.
It is an object of the present invention to provide a method for fabricating a 1T SRAM with a revised cell layout with a blocked P plus (P+) SID ion implant (I/I) on the cell storage node n-p junction.
The invention forms 1T Static Random Access Memory (SRAM) with a low concentration cell node region and a higher concentration bit line region (e.g., second bit line region).
To accomplish the above objectives, the present invention provides a structure for a 1T SRAM which is characterized:
a word line structure and a capacitor plate structure on a substrate; a cell node in the substrate between the word line structure and the capacitor plate structure; a bit line region in the substrate adjacent to the word line structure,
a capacitor plate structure is comprised of a capacitor dielectric on the substrate and a conductive plate layer on the capacitor dielectric; the capacitor plate structure overlying a plate region of the substrate; the plate region and the conductive plate layer acting as one plates of a capacitor;
the bit line region consists of a first bit line region and a second bit line (lightly doped) region; the first bit line region has the same impurity concentration as the cell node; the second bit line region has an impurity concentration (e.g., atoms/cc) greater than the cell node by preferably at least an order of 10.
The inventors have found an unexpected increase in the performance of the SRAM with the low concentration cell node region and the second (higher concentration) bit line. The inventors have found that the 1 T SRAM cell has performance degradation due to the high junction leakage on cell storage node. By blocking the P+ implant into the cell node, the n-p junction (cell node junction) leakage was reduced and the cell data retention time increased.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.